Each of these Schottky-clamped data selectors/multiplexers
contains inverters and drivers to supply fully complementary,
on-chip, binary decoding data selection to the
AND-OR gates. Separate output control inputs are provided
for each of the two four-line sections.
The 3-STATE outputs can interface directly with data lines
of bus-organized systems. With all but one of the common
outputs disabled (at a high impedance state), the low
impedance of the single enabled output will drive the bus
line to a HIGH or LOW logic level.
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