آي سي 7495 سجل إزاحة متوازي الوصول 4 بت

These 4-bit registers feature parallel and serial inputs, parallel
outputs, mode control, and two clock inputs. The registers
have three modes of operation.
Parallel (broadside) load
Shift right (the direction QA toward QD)
Shift left (the direction QD toward QA)
Parallel loading is accomplished by applying the four bits of
data and taking the mode control input high. The data is
loaded into the associated flip-flops and appears at the outputs
after the high-to-low transition of the clock-2 input. During
loading, the entry of serial data is inhibited.
Shift right is accomplished on the high-to-low transition of
clock 1 when the mode control is low; shift left is accomplished
on the high-to-low transition of clock 2 when the
mode control is high by connecting the output of each flipflop
to the parallel input of the previous flip-flop (QD to input
C, etc.) and serial data is entered at input D. The clock input
may be applied simultaneously to clock 1 and clock 2 if both
modes can be clocked from the same source.
Changes at the mode control input should normally be
made while both clock inputs are low; however, conditions
described in the last three lines of the truth table will also
ensure that register contents are protected.